Jonas Maebe a0e35fd1bc * synchronised with trunk till r42118 il y a 6 ans
..
a64att.inc 585e4a9a14 * corrected cosmetic ARM/AArch64 copy/paste leftovers (patch by il y a 10 ans
a64atts.inc 585e4a9a14 * corrected cosmetic ARM/AArch64 copy/paste leftovers (patch by il y a 10 ans
a64ins.dat c0548cadb0 * added some missing instructions and aliases, reordered them according il y a 10 ans
a64nop.inc 0197b84b7f + instruction table generator for arm64 il y a 13 ans
a64op.inc 585e4a9a14 * corrected cosmetic ARM/AArch64 copy/paste leftovers (patch by il y a 10 ans
a64reg.dat f1fb880f18 * fixed debug register values for vector registers il y a 10 ans
a64tab.inc 585e4a9a14 * corrected cosmetic ARM/AArch64 copy/paste leftovers (patch by il y a 10 ans
aasmcpu.pas 4357caaad8 * Removed unused local vars. il y a 7 ans
agcpugas.pas 281b3ad276 * fix case completeness and unreachable code warnings in compiler that would il y a 6 ans
aoptcpu.pas 281b3ad276 * fix case completeness and unreachable code warnings in compiler that would il y a 6 ans
aoptcpub.pas 281b3ad276 * fix case completeness and unreachable code warnings in compiler that would il y a 6 ans
aoptcpud.pas e1af3ecc5d + assembler optimizer unit skeleton il y a 13 ans
cgcpu.pas 281b3ad276 * fix case completeness and unreachable code warnings in compiler that would il y a 6 ans
cpubase.pas b41cd1eb6a * synchronised with trunk till r40575 il y a 6 ans
cpuinfo.pas f26ac9026e * enable LLVM support Linux/AArch64 il y a 6 ans
cpunode.pas f26ac9026e * enable LLVM support Linux/AArch64 il y a 6 ans
cpupara.pas 77658b925b * disable regular array -> dynamic array type coversion support unless il y a 6 ans
cpupi.pas 880d438704 * renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can il y a 8 ans
cputarg.pas 671d31df1d + Added support for the aarch64-android target. il y a 7 ans
hlcgcpu.pas b41cd1eb6a * synchronised with trunk till r40575 il y a 6 ans
itcpugas.pas 046184dfe9 + ARM64 GAS instruction table unit il y a 13 ans
ncpuadd.pas b821e31442 * force constants into a registers in the 32x32->64 optimized case il y a 10 ans
ncpucnv.pas 4357caaad8 * Removed unused local vars. il y a 7 ans
ncpuinl.pas 4357caaad8 * Removed unused local vars. il y a 7 ans
ncpumat.pas ada5060a34 * set pi_do_call for AArch64 mod/div nodes, as they call FPC_DIVBYZERO il y a 10 ans
ncpumem.pas 4686f61002 * keep track of the temp position separately from the offset in references, il y a 7 ans
ncpuset.pas 07bd4ba517 * let all the case code generation work with tconstexprint instead of aint, il y a 6 ans
ra64con.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers il y a 10 ans
ra64dwa.inc f1fb880f18 * fixed debug register values for vector registers il y a 10 ans
ra64nor.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers il y a 10 ans
ra64num.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers il y a 10 ans
ra64rni.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers il y a 10 ans
ra64sri.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers il y a 10 ans
ra64sta.inc f1fb880f18 * fixed debug register values for vector registers il y a 10 ans
ra64std.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers il y a 10 ans
ra64sup.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers il y a 10 ans
racpu.pas 281b3ad276 * fix case completeness and unreachable code warnings in compiler that would il y a 6 ans
racpugas.pas 281b3ad276 * fix case completeness and unreachable code warnings in compiler that would il y a 6 ans
rgcpu.pas 281b3ad276 * fix case completeness and unreachable code warnings in compiler that would il y a 6 ans
symcpu.pas 7dd1d6aa77 o fixes handling of iso i/o parameters/program parameters: il y a 10 ans