idct4x4_add_neon.c 5.0 KB

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  1. /*
  2. * Copyright (c) 2014 The WebM project authors. All Rights Reserved.
  3. *
  4. * Use of this source code is governed by a BSD-style license
  5. * that can be found in the LICENSE file in the root of the source
  6. * tree. An additional intellectual property rights grant can be found
  7. * in the file PATENTS. All contributing project authors may
  8. * be found in the AUTHORS file in the root of the source tree.
  9. */
  10. #include <arm_neon.h>
  11. void vpx_idct4x4_16_add_neon(
  12. int16_t *input,
  13. uint8_t *dest,
  14. int dest_stride) {
  15. uint8x8_t d26u8, d27u8;
  16. uint32x2_t d26u32, d27u32;
  17. uint16x8_t q8u16, q9u16;
  18. int16x4_t d16s16, d17s16, d18s16, d19s16, d20s16, d21s16;
  19. int16x4_t d22s16, d23s16, d24s16, d26s16, d27s16, d28s16, d29s16;
  20. int16x8_t q8s16, q9s16, q13s16, q14s16;
  21. int32x4_t q1s32, q13s32, q14s32, q15s32;
  22. int16x4x2_t d0x2s16, d1x2s16;
  23. int32x4x2_t q0x2s32;
  24. uint8_t *d;
  25. int16_t cospi_8_64 = 15137;
  26. int16_t cospi_16_64 = 11585;
  27. int16_t cospi_24_64 = 6270;
  28. d26u32 = d27u32 = vdup_n_u32(0);
  29. q8s16 = vld1q_s16(input);
  30. q9s16 = vld1q_s16(input + 8);
  31. d16s16 = vget_low_s16(q8s16);
  32. d17s16 = vget_high_s16(q8s16);
  33. d18s16 = vget_low_s16(q9s16);
  34. d19s16 = vget_high_s16(q9s16);
  35. d0x2s16 = vtrn_s16(d16s16, d17s16);
  36. d1x2s16 = vtrn_s16(d18s16, d19s16);
  37. q8s16 = vcombine_s16(d0x2s16.val[0], d0x2s16.val[1]);
  38. q9s16 = vcombine_s16(d1x2s16.val[0], d1x2s16.val[1]);
  39. d20s16 = vdup_n_s16(cospi_8_64);
  40. d21s16 = vdup_n_s16(cospi_16_64);
  41. q0x2s32 = vtrnq_s32(vreinterpretq_s32_s16(q8s16),
  42. vreinterpretq_s32_s16(q9s16));
  43. d16s16 = vget_low_s16(vreinterpretq_s16_s32(q0x2s32.val[0]));
  44. d17s16 = vget_high_s16(vreinterpretq_s16_s32(q0x2s32.val[0]));
  45. d18s16 = vget_low_s16(vreinterpretq_s16_s32(q0x2s32.val[1]));
  46. d19s16 = vget_high_s16(vreinterpretq_s16_s32(q0x2s32.val[1]));
  47. d22s16 = vdup_n_s16(cospi_24_64);
  48. // stage 1
  49. d23s16 = vadd_s16(d16s16, d18s16);
  50. d24s16 = vsub_s16(d16s16, d18s16);
  51. q15s32 = vmull_s16(d17s16, d22s16);
  52. q1s32 = vmull_s16(d17s16, d20s16);
  53. q13s32 = vmull_s16(d23s16, d21s16);
  54. q14s32 = vmull_s16(d24s16, d21s16);
  55. q15s32 = vmlsl_s16(q15s32, d19s16, d20s16);
  56. q1s32 = vmlal_s16(q1s32, d19s16, d22s16);
  57. d26s16 = vqrshrn_n_s32(q13s32, 14);
  58. d27s16 = vqrshrn_n_s32(q14s32, 14);
  59. d29s16 = vqrshrn_n_s32(q15s32, 14);
  60. d28s16 = vqrshrn_n_s32(q1s32, 14);
  61. q13s16 = vcombine_s16(d26s16, d27s16);
  62. q14s16 = vcombine_s16(d28s16, d29s16);
  63. // stage 2
  64. q8s16 = vaddq_s16(q13s16, q14s16);
  65. q9s16 = vsubq_s16(q13s16, q14s16);
  66. d16s16 = vget_low_s16(q8s16);
  67. d17s16 = vget_high_s16(q8s16);
  68. d18s16 = vget_high_s16(q9s16); // vswp d18 d19
  69. d19s16 = vget_low_s16(q9s16);
  70. d0x2s16 = vtrn_s16(d16s16, d17s16);
  71. d1x2s16 = vtrn_s16(d18s16, d19s16);
  72. q8s16 = vcombine_s16(d0x2s16.val[0], d0x2s16.val[1]);
  73. q9s16 = vcombine_s16(d1x2s16.val[0], d1x2s16.val[1]);
  74. q0x2s32 = vtrnq_s32(vreinterpretq_s32_s16(q8s16),
  75. vreinterpretq_s32_s16(q9s16));
  76. d16s16 = vget_low_s16(vreinterpretq_s16_s32(q0x2s32.val[0]));
  77. d17s16 = vget_high_s16(vreinterpretq_s16_s32(q0x2s32.val[0]));
  78. d18s16 = vget_low_s16(vreinterpretq_s16_s32(q0x2s32.val[1]));
  79. d19s16 = vget_high_s16(vreinterpretq_s16_s32(q0x2s32.val[1]));
  80. // do the transform on columns
  81. // stage 1
  82. d23s16 = vadd_s16(d16s16, d18s16);
  83. d24s16 = vsub_s16(d16s16, d18s16);
  84. q15s32 = vmull_s16(d17s16, d22s16);
  85. q1s32 = vmull_s16(d17s16, d20s16);
  86. q13s32 = vmull_s16(d23s16, d21s16);
  87. q14s32 = vmull_s16(d24s16, d21s16);
  88. q15s32 = vmlsl_s16(q15s32, d19s16, d20s16);
  89. q1s32 = vmlal_s16(q1s32, d19s16, d22s16);
  90. d26s16 = vqrshrn_n_s32(q13s32, 14);
  91. d27s16 = vqrshrn_n_s32(q14s32, 14);
  92. d29s16 = vqrshrn_n_s32(q15s32, 14);
  93. d28s16 = vqrshrn_n_s32(q1s32, 14);
  94. q13s16 = vcombine_s16(d26s16, d27s16);
  95. q14s16 = vcombine_s16(d28s16, d29s16);
  96. // stage 2
  97. q8s16 = vaddq_s16(q13s16, q14s16);
  98. q9s16 = vsubq_s16(q13s16, q14s16);
  99. q8s16 = vrshrq_n_s16(q8s16, 4);
  100. q9s16 = vrshrq_n_s16(q9s16, 4);
  101. d = dest;
  102. d26u32 = vld1_lane_u32((const uint32_t *)d, d26u32, 0);
  103. d += dest_stride;
  104. d26u32 = vld1_lane_u32((const uint32_t *)d, d26u32, 1);
  105. d += dest_stride;
  106. d27u32 = vld1_lane_u32((const uint32_t *)d, d27u32, 1);
  107. d += dest_stride;
  108. d27u32 = vld1_lane_u32((const uint32_t *)d, d27u32, 0);
  109. q8u16 = vaddw_u8(vreinterpretq_u16_s16(q8s16),
  110. vreinterpret_u8_u32(d26u32));
  111. q9u16 = vaddw_u8(vreinterpretq_u16_s16(q9s16),
  112. vreinterpret_u8_u32(d27u32));
  113. d26u8 = vqmovun_s16(vreinterpretq_s16_u16(q8u16));
  114. d27u8 = vqmovun_s16(vreinterpretq_s16_u16(q9u16));
  115. d = dest;
  116. vst1_lane_u32((uint32_t *)d, vreinterpret_u32_u8(d26u8), 0);
  117. d += dest_stride;
  118. vst1_lane_u32((uint32_t *)d, vreinterpret_u32_u8(d26u8), 1);
  119. d += dest_stride;
  120. vst1_lane_u32((uint32_t *)d, vreinterpret_u32_u8(d27u8), 1);
  121. d += dest_stride;
  122. vst1_lane_u32((uint32_t *)d, vreinterpret_u32_u8(d27u8), 0);
  123. return;
  124. }