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@@ -42,6 +42,10 @@ interface
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procedure second_float;override;
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end;
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+ tarmshlshrnode = class(tcgshlshrnode)
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+ procedure second_64bit;override;
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+ function first_shlshr64bitint: tnode; override;
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+ end;
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implementation
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@@ -291,9 +295,142 @@ implementation
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end;
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end;
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+ function tarmshlshrnode.first_shlshr64bitint: tnode;
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+ begin
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+ result := nil;
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+ end;
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+
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+ procedure tarmshlshrnode.second_64bit;
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+ var
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+ hreg64hi,hreg64lo,shiftreg:Tregister;
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+ v : TConstExprInt;
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+ l1,l2,l3:Tasmlabel;
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+ so: tshifterop;
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+
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+ procedure emit_instr(p: tai);
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+ begin
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+ current_asmdata.CurrAsmList.concat(p);
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+ end;
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+
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+ {Reg1 gets shifted and moved into reg2, and is set to zero afterwards}
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+ procedure shift_more_than_32(reg1, reg2: TRegister; shiftval: Byte ; sm: TShiftMode);
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+ begin
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+ shifterop_reset(so); so.shiftimm:=shiftval - 32; so.shiftmode:=sm;
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+ emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg1, so));
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+ emit_instr(taicpu.op_reg_const(A_MOV, reg1, 0));
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+ end;
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+
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+ procedure shift_less_than_32(reg1, reg2: TRegister; shiftval: Byte; shiftright: boolean);
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+ begin
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+ shifterop_reset(so); so.shiftimm:=shiftval;
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+ if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
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+ emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg1, reg1, so));
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+
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+ if shiftright then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
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+ so.shiftimm:=32-shiftval;
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+ emit_instr(taicpu.op_reg_reg_reg_shifterop(A_ORR, reg1, reg1, reg2, so));
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+
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+ if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
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+ so.shiftimm:=shiftval;
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+ emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg2, so));
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+ end;
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+
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+ procedure shift_by_variable(reg1, reg2, shiftval: TRegister; shiftright: boolean);
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+ var
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+ shiftval2:TRegister;
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+ begin
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+ shifterop_reset(so);
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+ shiftval2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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+ {Do we shift more than 32 bits?}
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+ emit_instr(setoppostfix(taicpu.op_reg_reg_const(A_RSB, shiftval2, shiftval, 32), PF_S));
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+
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+ {This part cares for 32 bits and more}
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+ emit_instr(setcondition(taicpu.op_reg_reg_const(A_SUB, shiftval2, shiftval, 32), C_MI));
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+ if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
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+ so.rs:=shiftval2;
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+ emit_instr(setcondition(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg1, so), C_MI));
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+
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+ {Less than 32 bits}
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+ so.rs:=shiftval;
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+ emit_instr(setcondition(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg2, so), C_PL));
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+ if shiftright then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
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+ so.rs:=shiftval2;
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+ emit_instr(setcondition(taicpu.op_reg_reg_reg_shifterop(A_ORR, reg2, reg2, reg1, so), C_PL));
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+
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+ {Final adjustments}
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+ if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
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+ so.rs:=shiftval;
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+ emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg1, reg1, so));
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+ end;
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+
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+ begin
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+ location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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+
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+ { load left operator in a register }
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+ hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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+ hreg64hi:=left.location.register64.reghi;
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+ hreg64lo:=left.location.register64.reglo;
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+ location.register64.reghi:=hreg64hi;
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+ location.register64.reglo:=hreg64lo;
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+
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+ { shifting by a constant directly coded: }
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+ if (right.nodetype=ordconstn) then
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+ begin
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+ v:=Tordconstnode(right).value and 63;
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+ {Single bit shift}
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+ if v = 1 then
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+ if nodetype=shln then
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+ begin
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+ {Shift left by one by 2 simple 32bit additions}
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+ emit_instr(setoppostfix(taicpu.op_reg_reg_reg(A_ADD, hreg64lo, hreg64lo, hreg64lo), PF_S));
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+ emit_instr(taicpu.op_reg_reg_reg(A_ADC, hreg64hi, hreg64hi, hreg64hi));
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+ end
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+ else
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+ begin
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+ {Shift right by first shifting hi by one and then using RRX (rotate right extended), which rotates through the carry}
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+ shifterop_reset(so); so.shiftmode:=SM_LSR; so.shiftimm:=1;
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+ emit_instr(setoppostfix(taicpu.op_reg_reg_shifterop(A_MOV, hreg64hi, hreg64hi, so), PF_S));
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+ so.shiftmode:=SM_RRX; so.shiftimm:=0; {RRX does NOT have a shift amount}
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+ emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, hreg64lo, hreg64lo, so));
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+ end
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+ {A 32bit shift just replaces a register and clears the other}
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+ else if v = 32 then
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+ begin
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+ if nodetype=shln then
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+ emit_instr(taicpu.op_reg_const(A_MOV, hreg64hi, 0))
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+ else
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+ emit_instr(taicpu.op_reg_const(A_MOV, hreg64lo, 0));
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+ location.register64.reghi:=hreg64lo;
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+ location.register64.reglo:=hreg64hi;
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+ end
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+ {Shift LESS than 32}
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+ else if v < 32 then
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+ if nodetype=shln then
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+ shift_less_than_32(hreg64hi, hreg64lo, v.uvalue, false)
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+ else
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+ shift_less_than_32(hreg64lo, hreg64hi, v.uvalue, true)
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+ {More than 32}
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+ else
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+ if nodetype=shln then
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+ shift_more_than_32(hreg64lo, hreg64hi, v.uvalue, SM_LSL)
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+ else
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+ shift_more_than_32(hreg64hi, hreg64lo, v.uvalue, SM_LSR)
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+ end
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+ else
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+ begin
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+ { force right operators in a register }
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+ hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,resultdef,false);
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+ if nodetype = shln then
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+ shift_by_variable(hreg64lo,hreg64hi,right.location.register, false)
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+ else
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+ shift_by_variable(hreg64hi,hreg64lo,right.location.register, true);
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+ end;
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+ end;
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+
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begin
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cmoddivnode:=tarmmoddivnode;
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cnotnode:=tarmnotnode;
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cunaryminusnode:=tarmunaryminusnode;
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+ cshlshrnode:=tarmshlshrnode;
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end.
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marco