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aasmcpu.pas
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017d58748f
Use thumb_func flag to detect selected arm/thumb mode.
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%!s(int64=9) %!d(string=hai) anos |
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agarmgas.pas
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9d1646e2a8
Add support for writeback in RFE and SRS instructions.
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%!s(int64=9) %!d(string=hai) anos |
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aoptcpu.pas
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1266491085
o refactored some peephole optimizer code:
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%!s(int64=9) %!d(string=hai) anos |
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aoptcpub.pas
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d37e72dbf9
* ARM: instructions do modify the base register of pre/postindexed references. Report this fact in spilling_get_operation_type_ref and RegModifiedByInstruction functions.
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%!s(int64=11) %!d(string=hai) anos |
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aoptcpuc.pas
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790a4fe2d3
* log and id tags removed
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%!s(int64=20) %!d(string=hai) anos |
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aoptcpud.pas
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790a4fe2d3
* log and id tags removed
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%!s(int64=20) %!d(string=hai) anos |
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armatt.inc
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9d1646e2a8
Add support for writeback in RFE and SRS instructions.
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%!s(int64=9) %!d(string=hai) anos |
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armatts.inc
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9d1646e2a8
Add support for writeback in RFE and SRS instructions.
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%!s(int64=9) %!d(string=hai) anos |
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armins.dat
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9d1646e2a8
Add support for writeback in RFE and SRS instructions.
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%!s(int64=9) %!d(string=hai) anos |
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armnop.inc
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439027a8de
Add most pre-UAL VFP instruction forms.
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%!s(int64=10) %!d(string=hai) anos |
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armop.inc
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9d1646e2a8
Add support for writeback in RFE and SRS instructions.
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%!s(int64=9) %!d(string=hai) anos |
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armreg.dat
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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armtab.inc
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439027a8de
Add most pre-UAL VFP instruction forms.
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%!s(int64=10) %!d(string=hai) anos |
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cgcpu.pas
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3f2057a2f2
* do not generate blx instructions, the generation of blx instead of bl was introduced some years ago but today it proves to be wrong: if necessary, the linker converts the bl into a blx, this is also how gcc and clang handle it
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%!s(int64=9) %!d(string=hai) anos |
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cpubase.pas
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5ca1740bee
Fix issue in is_thumb32_imm. imm<11:10> have to be non-zero meaning the rotate only works from 8 to 31. Caused 0x8000001F to be mistaken for a valid immediate.
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%!s(int64=10) %!d(string=hai) anos |
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cpuelf.pas
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1b02dd27dc
Make relocation type more precise compared to output of gas.
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%!s(int64=9) %!d(string=hai) anos |
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cpuinfo.pas
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9aa3c23b18
Added a bunch of new and fixed embedded controller units. From Michael Ring.
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%!s(int64=9) %!d(string=hai) anos |
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cpunode.pas
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b57c95043f
+ support overriding tdef/tsym methods with target-specific functionality:
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%!s(int64=11) %!d(string=hai) anos |
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cpupara.pas
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fa3b0ca312
* support marking defs created via the getreusable*() class methods as
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%!s(int64=9) %!d(string=hai) anos |
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cpupi.pas
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f2c8824963
* ARM: Do not use R9 as a fixed GOT register.
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%!s(int64=10) %!d(string=hai) anos |
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cputarg.pas
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d26f0552a0
* Sync with trunk r23404.
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%!s(int64=12) %!d(string=hai) anos |
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hlcgcpu.pas
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432248cbf1
* Removed lot of unused vars.
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%!s(int64=10) %!d(string=hai) anos |
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itcpugas.pas
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47d43750e4
* remove unused units from uses statements
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%!s(int64=12) %!d(string=hai) anos |
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narmadd.pas
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297c17d4f0
Add missing prefix for VCMP for FPv4_S16.
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%!s(int64=10) %!d(string=hai) anos |
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narmcal.pas
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8b8a786823
* moved ARM/x86 ifdef'ed code from ncgcal to virtual methods
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%!s(int64=12) %!d(string=hai) anos |
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narmcnv.pas
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0fc1fd6ac1
* replaced current_procinfo.currtrue/falselabel with storing the true/false
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%!s(int64=10) %!d(string=hai) anos |
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narmcon.pas
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b0ff41406a
* grouped all tai_real* types into a single tai_realconst type,
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%!s(int64=11) %!d(string=hai) anos |
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narminl.pas
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432248cbf1
* Removed lot of unused vars.
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%!s(int64=10) %!d(string=hai) anos |
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narmmat.pas
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432248cbf1
* Removed lot of unused vars.
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%!s(int64=10) %!d(string=hai) anos |
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narmmem.pas
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d6de2c03cb
* generic part of r26050 from the hlcgllvm branch: made tcgvecnode hlcg-safe
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%!s(int64=10) %!d(string=hai) anos |
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narmset.pas
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da696057ab
* converted register_maybe_adjust_setbase() to the high level code generator
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%!s(int64=9) %!d(string=hai) anos |
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pp.lpi.template
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1f032375c3
* improved template with help from Mattias Gaertner
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%!s(int64=19) %!d(string=hai) anos |
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raarm.pas
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780e75bfac
o patch by Jeppe Johansen to fix mantis #17472:
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%!s(int64=14) %!d(string=hai) anos |
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raarmgas.pas
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37cb35d780
+ support for the .code directive in arm inline assembler
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%!s(int64=9) %!d(string=hai) anos |
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rarmcon.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmdwa.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmnor.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmnum.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmrni.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmsri.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmsta.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmstd.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmsup.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rgcpu.pas
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432248cbf1
* Removed lot of unused vars.
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%!s(int64=10) %!d(string=hai) anos |
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symcpu.pas
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7dd1d6aa77
o fixes handling of iso i/o parameters/program parameters:
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%!s(int64=10) %!d(string=hai) anos |
florian
1266491085
o refactored some peephole optimizer code: