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a64att.inc
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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a64atts.inc
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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a64ins.dat
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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a64nop.inc
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0197b84b7f
+ instruction table generator for arm64
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13 years ago |
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a64op.inc
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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a64reg.dat
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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a64tab.inc
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585e4a9a14
* corrected cosmetic ARM/AArch64 copy/paste leftovers (patch by
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10 years ago |
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aasmcpu.pas
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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agcpugas.pas
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b8e6610617
Add explicit longint typecast to avoid range check errors with unwindrec longword variable
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4 years ago |
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aoptcpu.pas
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eec51afadd
* patch (with little modification) by J. Gareth Moreton: refactor ARM/Aarch64 peephole optimizer, first part of #37526
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4 years ago |
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aoptcpub.pas
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281b3ad276
* fix case completeness and unreachable code warnings in compiler that would
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6 years ago |
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aoptcpud.pas
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e1af3ecc5d
+ assembler optimizer unit skeleton
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13 years ago |
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cgcpu.pas
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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cpubase.pas
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3f19bd693f
+ Add new LastCommonAsmOp constant to arm and aarch64 CPU targets.
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4 years ago |
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cpuinfo.pas
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592df7fa59
* disable cs_opt_regvar on all platforms when compiled for LLVM (LLVM does
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5 years ago |
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cpunode.pas
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2b59000d56
+ implement compiler support for SEH on Win64
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5 years ago |
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cpupara.pas
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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cpupi.pas
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2b59000d56
+ implement compiler support for SEH on Win64
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5 years ago |
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cputarg.pas
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3af74d2fd2
+ implement initial compiler support for Win64 on Aarch64
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5 years ago |
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hlcgcpu.pas
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637976e83f
* patch by Marģers to unify internal error numbers, resolves #37888
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4 years ago |
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itcpugas.pas
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046184dfe9
+ ARM64 GAS instruction table unit
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13 years ago |
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ncpuadd.pas
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078595be4c
+ support for software floating point exception handling on AArch64 (-CE)
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6 years ago |
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ncpucnv.pas
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4357caaad8
* Removed unused local vars.
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6 years ago |
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ncpucon.pas
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a019536cd5
* avoid that -0.0 is handled by the eor optimization
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6 years ago |
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ncpuflw.pas
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637976e83f
* patch by Marģers to unify internal error numbers, resolves #37888
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4 years ago |
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ncpuinl.pas
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078595be4c
+ support for software floating point exception handling on AArch64 (-CE)
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6 years ago |
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ncpumat.pas
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28f25b2df0
* reworked usage of tcgnotnode.handle_locjump
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5 years ago |
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ncpumem.pas
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4686f61002
* keep track of the temp position separately from the offset in references,
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7 years ago |
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ncpuset.pas
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7f4b94e408
* generate jump tables into the same section as the code as otherwise we'll get bogus relocations (in case of clang.exe) or a future support for armasm64.exe will reject the relative symbols outright
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5 years ago |
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ra64con.inc
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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ra64dwa.inc
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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ra64nor.inc
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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ra64num.inc
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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ra64rni.inc
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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ra64sri.inc
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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ra64sta.inc
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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ra64std.inc
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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ra64sup.inc
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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racpu.pas
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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racpugas.pas
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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4 years ago |
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rgcpu.pas
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13cb57b2c3
+ Aarch64: trgcpu.get_spill_subreg: return MM sub register correctly, resolves #37393
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5 years ago |
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symcpu.pas
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7dd1d6aa77
o fixes handling of iso i/o parameters/program parameters:
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10 years ago |
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tripletcpu.pas
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eb7ba1690e
* mark all external assemblers using an LLVM tool using af_llvm
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5 years ago |
pierre
b8e6610617
Add explicit longint typecast to avoid range check errors with unwindrec longword variable