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aasmcpu.pas
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20dbda751a
* fixed sparc compilation after addr_lo/hi changes
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18 years ago |
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aoptcpu.pas
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b70c5efa65
* SPARC peephole: check that result of GetNextInstructionUsingReg is actually an instruction, because GetNextInstruction can stop at a label. Resolves #26798.
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10 years ago |
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aoptcpub.pas
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2f5ce095ce
* RefsHaveIndexReg -> cpurefshaveindexreg
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13 years ago |
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aoptcpud.pas
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790a4fe2d3
* log and id tags removed
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20 years ago |
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cgcpu.pas
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e4fea2ebc8
* Dummy implementations of a_bit_scan_reg_reg and g_stackpointer_alloc in tcg, removes the need to override these methods in every descendant code generator solely to avoid "constructing a class with abstract method" warning.
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11 years ago |
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cpubase.pas
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f3801d13de
* SPARC: cleaned up and actualized TAsmCond (stuff copy-pasted from x86 removed, conditions for unordered floating-point comparisons added). Fixes Mantis #9362 on this target.
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11 years ago |
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cpuelf.pas
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0aa7204707
+ Added codes of dynamic relocations to TElfTarget; since most targets use similar dynamic relocation model differing only in code values, this will allow to do majority of handling in the base class.
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12 years ago |
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cpugas.pas
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5e6669890a
Handle asmextraopt in powerpc, mips and sparc assemblers
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11 years ago |
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cpuinfo.pas
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e190f76dd9
* removed spaces from sparc cpu name strings so they can be much easier used
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12 years ago |
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cpunode.pas
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b57c95043f
+ support overriding tdef/tsym methods with target-specific functionality:
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11 years ago |
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cpupara.pas
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2c02e8a726
- i386, x86_64, SPARC: removed paramanager.getintparaloc overrides, it is handled by generic implementation since r24716.
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11 years ago |
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cpupi.pas
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176d8434e4
* SPARC: completely rewrote PIC-related code, got it twice shorter in source lines and much less instructions in generated code.
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11 years ago |
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cputarg.pas
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7587145320
Add possibility to test sparc elf generator with -dTEST_AGSPARC_ELF
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13 years ago |
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hlcgcpu.pas
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72e9cfee24
* create/destroy also the high level code generator for all architectures,
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14 years ago |
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itcpugas.pas
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790a4fe2d3
* log and id tags removed
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20 years ago |
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ncpuadd.pas
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0cf7357ee2
* fix GetResFlags DFA optimizer warning on Sparc and AVR too
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11 years ago |
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ncpucall.pas
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58882e2934
* SPARC: UNIMP instruction has 22-bit "opcode", not 12-bit.
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11 years ago |
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ncpucnv.pas
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4065483a50
* completed thlcgobj.location_force_fpureg(), use it everywhere and removed
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11 years ago |
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ncpuinln.pas
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4065483a50
* completed thlcgobj.location_force_fpureg(), use it everywhere and removed
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11 years ago |
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ncpumat.pas
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f3801d13de
* SPARC: cleaned up and actualized TAsmCond (stuff copy-pasted from x86 removed, conditions for unordered floating-point comparisons added). Fixes Mantis #9362 on this target.
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11 years ago |
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ncpuset.pas
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e163a2c813
* MIPS and SPARC: determine whether case expression is in range using a single unsigned comparison (like it is done on other targets).
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11 years ago |
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opcode.inc
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9a486d73ba
+ SPARC: support FNEGd/FNEGq internal instructions, and use them to implement floating-point negation more efficiently.
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11 years ago |
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racpu.pas
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18eb495d0f
* give a regular error message instead of an internal error on x86
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17 years ago |
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racpugas.pas
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eaba90dda7
* SPARC: since peephole optimizer recognizes only one conditional branching instruction, generate all branches using A_Bxx opcode, and change it to A_FBxx if necessary when writing assembler. This enables optimization of floating-point branches.
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11 years ago |
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rgcpu.pas
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d2a9308181
+ SPARC: implemented register spill replacement.
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11 years ago |
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rspcon.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspdwrf.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspnor.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspnum.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rsprni.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspsri.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspstab.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspstd.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspsup.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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spreg.dat
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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strinst.inc
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9a486d73ba
+ SPARC: support FNEGd/FNEGq internal instructions, and use them to implement floating-point negation more efficiently.
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11 years ago |
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symcpu.pas
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02495c17bd
Fix a typo. The CPU specific version of "ttypesym" should be called "tcputypesym" and not "tcpuypesym".
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11 years ago |
sergei
b70c5efa65
* SPARC peephole: check that result of GetNextInstructionUsingReg is actually an instruction, because GetNextInstruction can stop at a label. Resolves #26798.