Jonas Maebe d34e0b091b * fixed aarch64 shifterop parsing in inline assembly 6 years ago
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a64att.inc 585e4a9a14 * corrected cosmetic ARM/AArch64 copy/paste leftovers (patch by 10 years ago
a64atts.inc 585e4a9a14 * corrected cosmetic ARM/AArch64 copy/paste leftovers (patch by 10 years ago
a64ins.dat c0548cadb0 * added some missing instructions and aliases, reordered them according 10 years ago
a64nop.inc 0197b84b7f + instruction table generator for arm64 12 years ago
a64op.inc 585e4a9a14 * corrected cosmetic ARM/AArch64 copy/paste leftovers (patch by 10 years ago
a64reg.dat f1fb880f18 * fixed debug register values for vector registers 10 years ago
a64tab.inc 585e4a9a14 * corrected cosmetic ARM/AArch64 copy/paste leftovers (patch by 10 years ago
aasmcpu.pas 4357caaad8 * Removed unused local vars. 6 years ago
agcpugas.pas 4643a0b1ff * Register external gas assembler for aarch64-android and x86_64-android. 6 years ago
aoptcpu.pas 4357caaad8 * Removed unused local vars. 6 years ago
aoptcpub.pas 9b0ff05ee8 - get rid of MaxOps, it is redundant with max_operands 6 years ago
aoptcpud.pas e1af3ecc5d + assembler optimizer unit skeleton 12 years ago
cgcpu.pas 4357caaad8 * Removed unused local vars. 6 years ago
cpubase.pas 820d2f7135 * support OS_32/OS_64 in AArch64 cgsize2subreg() for MM registers (can happen 6 years ago
cpuinfo.pas 73c46a5988 - removed unused constants 8 years ago
cpunode.pas a0efde8167 * automatically generate necessary indirect symbols when a new assembler 9 years ago
cpupara.pas 8b9e90dc7a * keep track of whether a routine has a C-style variadic parameter in the 6 years ago
cpupi.pas 880d438704 * renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can 8 years ago
cputarg.pas 671d31df1d + Added support for the aarch64-android target. 6 years ago
hlcgcpu.pas 52fec8a94a * when optimising subsetreg moves for aarch64, take into account the fact 6 years ago
itcpugas.pas 046184dfe9 + ARM64 GAS instruction table unit 12 years ago
ncpuadd.pas b821e31442 * force constants into a registers in the 32x32->64 optimized case 10 years ago
ncpucnv.pas 4357caaad8 * Removed unused local vars. 6 years ago
ncpuinl.pas 4357caaad8 * Removed unused local vars. 6 years ago
ncpumat.pas ada5060a34 * set pi_do_call for AArch64 mod/div nodes, as they call FPC_DIVBYZERO 10 years ago
ncpumem.pas 4686f61002 * keep track of the temp position separately from the offset in references, 7 years ago
ncpuset.pas 07bd4ba517 * let all the case code generation work with tconstexprint instead of aint, 6 years ago
ra64con.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers 10 years ago
ra64dwa.inc f1fb880f18 * fixed debug register values for vector registers 10 years ago
ra64nor.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers 10 years ago
ra64num.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers 10 years ago
ra64rni.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers 10 years ago
ra64sri.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers 10 years ago
ra64sta.inc f1fb880f18 * fixed debug register values for vector registers 10 years ago
ra64std.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers 10 years ago
ra64sup.inc 9c55fa6f6c + FPCR, FPSR and TPIDR registers 10 years ago
racpu.pas 558b8967b6 + Aarch64 assembler reader 10 years ago
racpugas.pas d34e0b091b * fixed aarch64 shifterop parsing in inline assembly 6 years ago
rgcpu.pas 4686f61002 * keep track of the temp position separately from the offset in references, 7 years ago
symcpu.pas 7dd1d6aa77 o fixes handling of iso i/o parameters/program parameters: 10 years ago